26 Jun/20
14:30 - 15:45 (Europe/Zurich)

ADTObsBox - Experiment-scale data analysis of the transverse positional data in the LHC



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ADTObsBox - Experiment-scale data analysis of the transverse positional data in the LHC


The ADT (LHC Transverse Damper) is the only place in the LHC where the bunch-by-bunch transverse position is available at full rate and with a submicron resolution. This information is invaluable for the beam physicists or various beam diagnostics through the cycle.

The ADT has 16 beam position modules (4 per beam, per plane), each producing a 1 Gb/s data stream. This results in a combined data transfer rate of 2 GB/s which is similar to the HLT readout in the LHC experiments. To fully utilize the beam data, a powerful data acquisition system called ADTObsBox (LHC Transverse Damper Observation Box) was introduced in 2015.

The system has gradually expanded from supplying only raw data buffers, to performing various online analysis (e.g. real-time transverse instability detection). This made the system evolve into an important operational tool for LHC during RUN 2 and it is expected to become an even more viable resource during RUN 3, as the number of applications grows constantly. To cope with the new demand and to exploit the full potential of the system, a new, more powerful successor has been developed during LS2.

A new PCIe based multi-channel IO card, capable of pre-processing the data in the FPGA was developed using COTS hardware. It is accompanied by a high-performance asynchronous multi-process driver. Through high-level libraries, multiple applications can access the data concurrently and the first tests demonstrated that these applications can read the data with a latency close to one LHC turn (a factor 3300 lower than the previous system).

A multitude of new features and possibilities were introduced, such as a 24-hour circular buffer using local hard-drives, or using GPGPUs to accelerate computationally intensive applications.

The presentation will give you an insight into the complete process of developing a high-performance computing system for digital signal processing by the equipment groups, utilizing COTS hardware components and writing highly optimized FPGA firmware with supporting Linux drivers and high-level software.